Voids within metal interconnect structures, such as those in integrated circuits, can have different sizes, distributions and locations within the interconnect structures. For example, voids can range from “monster” voids occluding whole lines, vias or contacts with immediate yield impact, to small voids within lines, vias or contacts that impact the long-term reliability of the device. Voids can be uniformly distributed within a line, via or contact section or they can be localized in deep or shallow portions of a line, via or contact.
Void formation can stem from a number of different root causes. For example, a void can form during a metal film deposition process where there is poor step coverage, typically resulting in a slit shaped void in the middle of via or contact regions. A void can also form from the scratching of metal surfaces during chemical mechanical polishing (CMP) with subsequent metal deposition, typically resulting in a shallow, long void in the upper portion of a via and line. Other examples include voids caused during the high temperature annealing process of metal film and during trench and via etching. If one could characterize the size, distribution and location of voids, one could gain information about the root causes of the voids.
Traditionally, the only way to know the size, distribution and location of voids is by using destructive methods such as Focused Ion Beam (FIB) cross-sectioning techniques. Although these techniques can help verify the existence of voids, the sample is destroyed during the analysis. This is expensive for integrated circuit manufacturers since it means sacrificing product samples from the product line and often results in wasting product found to have no significant defects. Furthermore, FIB techniques are time consuming, which can cause downtime of the product line production. This can be an especially big problem if numerous scans on numerous wafers are needed to ensure void-free processing.
Accordingly, there is a need to characterize voids that may reside within integrated circuit product lines efficiently and without sacrificing valuable product.